1. Field of the Invention
This invention relates generally to logic gates. More particularly, the invention relates to a high-fanin NOR gate that does not require a synchronization event before the output can be sampled.
2. Related Art
In digital circuits, it is often necessary to generate the logical NOR of a large number of input signals. Such circuits with a large number of inputs are often referred to as high fanin circuits. Example circuits include zero detect circuits in Arithmetic Logic Units (ALUs), Cache Tag Comparators, and Programmable Logic Arrays, where the number of inputs can be 16 or more.
For power and speed considerations, the conventional implementation of such a NOR logic gate is a dynamic MOS NOR circuit. The output node of the dynamic MOS NOR circuit is pre-charged to a known high state. If any input to the circuit is active (or true or logic "1"), the output switches to a low state.
A scenario of special interest is that in which all the circuit inputs are inactive, as in the case of a zero detector designed to detect all zeroes for a number of input signals. In this case, the conventional MOS NOR gate makes no state change on its output. Therefore, it is difficult to distinguish the pre-charged state from the evaluated, all zero input state by observing only the output. Often, it is necessary for an external agent to make the distinction based on an elapsed time period. For example, once the output pre-charge is complete, the external agent observes the output node after an elapsed time-period. If the output is still in the pre-charged state, then the logic gate has probably evaluated a complete set of inputs, and the all-zero case is in effect. The arbitrary point (in time) of evaluation is often referred to as a synchronization point or a synchronization event.
The issue is how much elapsed time is enough before the synchronization event? If the elapsed time interval is too short, then the circuit output might be erroneously sampled before all the inputs have been updated. If the interval is too long, then valuable time is wasted. As processor clock frequencies increase, it is extremely important not to waste time in delay paths.